ADAS and autonomous driving applications are increasingly dependent on the high-performance computing of SoCs. Reaching gigahertz clock frequencies and offering image processors and other accelerators, they appear to provide the performance required for vision systems.

 However, with all application elements integrated, challenges start to arise with the system failing to respond in time under all test conditions.

 When reviewing such failed tests, INCHRON’s team typically find one cause is the memory bandwidth limitations of the interconnects between processors, accelerators, and memories. Traditionally, this well-known SoC bottleneck has not been included in system models.

 Today in chronSUITE 3.0, the industry’s leading timing toolkit, development teams can visualize the utilization of both processors and interconnects. As a result, application code priorities and execution order can be modified to ensure that both processor load and interconnect bandwidth limits are not exceeded.

Discover how developers use chronSUITE 3.0 to develop complex vision systems in our latest article on the topic here:


Dr. Ralf Münzenberger and Matthias Dörfel

When function meets time

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