INCHRON Teams Up with Arm to Predict Software Real-Time Behavior when Migrating to SoCs

The change in Electrical/Electronic (E/E) architectures is changing how software applications are being developed. Where traditionally a function was integrated into a dedicated electronic control unit (ECU), that function may now be part of a larger high-performance computing (HPC) platform or split across several computing devices. This changes how software for automotive is developed, requiring careful attention to software timing and event chains from the earliest stages of the development process.

Of course, no one is starting with a clean slate. OEMs and their suppliers are looking to reuse the software they built for traditional ECUs before migrating to new hardware. This requires an excellent understanding of execution time, processor load, memory needs, and interface bandwidth.

Model-based system engineering methodologies are ideal for tackling the complexity of this challenge, enabling development teams to select the optimal System-on-Chip (SoC) or microcontroller (MCU) for the system.

Across the automotive industry, the primary goal is to decouple software from hardware. This will simplify software updates in the field and enable OEMs to provide software-based feature upgrades throughout the vehicle’s life. To achieve this, vehicles are deploying powerful processing platforms that utilize heterogeneous system-on-chip (SoC) devices or high-end real-time microcontrollers (MCUs), thereby reducing the number of ECUs and cabling.
The ultimate goal is to achieve software-defined vehicles (SDVs) that allow any software to be run almost anywhere, even if it is distributed across multiple processing platforms. While this is a noble objective, it is fraught with challenges as the vehicle has some unique requirements compared to other distributed computing systems, including functional safety coupled with cybersecurity and limited memory resources.

Predicting behavior with model-based simulation
As development teams explore mapping existing functionality to an SDV’s processor, it requires more than a DMIPS-to-DMIPS comparison. This means a holistic understanding is needed, covering everything from execution time and processor load to communication mechanisms and real-time operating system (RTOS) overheads. Developers need to break down these end-to-end timing requirements into event chains, typically from sensor to actuator, to effectively manage such complexity.

Model-based simulation offers development teams a formal method for predicting behavior and identifying potential issues. Simulators, such as INCHRON’s chronSIM, can utilize models to run simulations from a high level down to individual event chains passing through a single processor. This includes scenarios where software is executed on an RTOS or hypervisor and can be repeated for a multitude of activation patterns, accommodating the effects of preemption, interrupts, and interference between tasks.
Perhaps the most significant advantage of this approach is that it can be undertaken repeatedly before any hardware has been selected.

Acquiring timing data is the first challenge with this approach. Most development teams have an inherent understanding of their system’s timing at a high level, such as the minimum time required to bring a vehicle to a standstill when performing emergency braking. They may also be able to break this down into the execution time of software elements during this process, which is a great starting point when constructing a model.
However, to migrate software from the existing processor core to a new target core, in many cases, it is essential to understand the precise execution time. This is achieved by collecting trace data for the existing system and processor. From this, a simplified real-time model can be generated that includes the net execution behavior and activation scheme for each process, interrupt, and function.

By drawing upon a library of processor models, it is now possible to explore the net execution times of that same software on alternative processors, attaining a more realistic understanding of performance regardless of whether the code is numerically or flow-control intensive.
Even the addition of a hypervisor can be factored into this approach. This enables the team to explore different time partitioning approaches (number, order, length of time) and their impact on response times and end-to-end latency. The same applies to preemptive priority-based hypervisors.

Together with its partner Arm, INCHRON collaborates on the development of models that support automotive software developers as they tackle precisely such software migration challenges. It is intended that this will help teams operate with precise timing requirements and utilize event chains as they transition from a world of individual ECUs to highly complex SDVs running hypervisors.
Not only does this approach facilitate the selection of a range of high-performance MCUs and SoCs, but it also integrates timing performance as a metric for both internal and external teams. This metric can be utilized from project kick-off through to the start of production to identify and resolve timing issues as they arise.

More on INCHRON’s participation in the Arm Partner Ecosystem is available here: https://www.arm.com/partners/catalog/inchron-ag