Unleash the Power of Timing Simulation
Simulate the behavior of real-time embedded systems. Easily compare different designs, verify timing and performance requirements, and check reliability and robustness for safety-critical applications. Predict and fix potentially severe errors 12 months earlier.
For architects, developers, and integrators.
Simulate before You Have Hardware
chronSIM is a simulation tool for real-time embedded systems. It uses an integrated model of the hardware and software to predict the timing and performance of processes in a real-time operating system, taking into account the effects of time synchronization and drifting physical clocks.
The output of the simulation is an event trace that can be displayed and analyzed in chronVIEW, the same as reviewing a hardware trace.
Sensor Data Fusion in High-Performance Domain Controllers
Understanding the Effects of Clock Drift and Asynchronicity
Migration to Multicore and High-Performance SoCs
Model-Based Simulation of Safety-Critical Automotive Control Systems
Verification of Timing and Performance Requirements
End-to-End Analysis of Distributed Functions in Vehicle Networks
Visualization and Statistical Evaluation of Trace Data
Design Space Exploration and Optimization
- Simulation of RTOS scheduling and heterogeneous SoC hardware architectures
- Simulation of memory congestion effects in multicore environments with shared memory … read more
- Simulation of queued communication and event chains
- Simulation of LIN, CAN, FlexRay, and Ethernet networks
- Simulation of corner cases
- Specification of complex stimulation scenarios
- Importer for OSEK, CAN DBC, Fibex, AUTOSAR, and APP4MC AMALTHEA models
- Model generation and workflow automation (EMF Ecore, Python, CI / Batch, REST API)
- Supports the FMI standard for co-simulation
“Real-time simulation with chronSIM supports and improves the development process. We detect timing errors in early development phases. In addition, we have greater trust because of improved system understanding.”
“In the tender phase, the combination of architectural modeling (SysML / UML) and evaluation with INCHRON’s chronSUITE has several advantages.“
Dr. Jan Meyer, Hella KGaA Hueck & Co.
Processes, methodology and tools
Modeling of Heterogeneous SoC Hardware Architectures
- Single-core, multicore processors, hardware accelerators, and SoCs / multi-processor systems
- Memories and caches
- Memory buses / interconnects with QoS parameters
Simulation of Memory Bus Congestion Effects in Multicore Environments
- Based on the specification of the internal behavior and the hardware architecture, read and write accesses are simulated considering the data size and mapping, the bandwidth of interconnects, and the processing capacity of the individual cores.
- Prediction of performance bottlenecks in highly loaded memory bus scenarios
- Use simulation results to optimize the allocation of CPU, memory resources, and scheduling.
Modeling of Software Components
- Simple component model that encapsulates data and functions.
- Supports multiple levels of abstraction for modeling the internal behavior of functions such as probability distributions, call graphs, and C/C++ code.
Modeling of Queued Communication and Event Chains
- Modeling of communication links as queues with different access policies
- Dedicated call graph items to accurately model the timing of communication within the control flow.
- Modeling of the routing of signals between inputs and outputs within a call graph
- By querying mode variables, the communication can be modeled depending on the current system status. This is required for simulating data flows in ADAS and AD systems.
- Strict separation between the specification of a data flow and its observation in the trace
- Uniform evaluation of measured and simulated traces
Modeling the Execution Behavior of Processes and Functions
- Call graph model based on the activity graph model from APP4MC AMALTHEA
- Definition of modes and mode-dependent execution branches
- Call graph primitives for inter-process communication such as events, semaphores, and spinlocks
- Definition of counters and operators for manipulating counters
- Modeling of explicit and rate-based data accesses
- Support of C / C++ as a modeling language
- Simulation of RTOS scheduling: preemptive, cooperative, fixed-priority, EDF, round-robin, TDMA, hypervisor
- OSEK, AUTOSAR, ARINC-653, QNX, GHS Integrity, PikeOS, Linux, ThreadX
- Prediction of scheduling effects and timing violations
- Simulation of time synchronization and drifting clocks in distributed systems
- Simulation of multithreaded applications … read more
- Modeling of complex stimulation scenarios
- C / C++ API for simulation of custom (user-defined) scheduling strategies
Simulation of Peripherals and Bus Communication
- Simulation of bus communication for LIN, CAN, FlexRay, and Ethernet
- Simulation of internet and transport layer protocols (TCP / UDP over IPv4 / IPv6)
- Protocol-stack parameters, QoS, VLAN, etc.
- End-to-end event chain analysis for ADAS and AD systems
- C / C++ API for simulation
“INCHRON enables Valeo to start validation of our architectural designs at the logical level, facilitating identification of potential problems during the earliest stages of development. This allows us to define the integration requirements for derived projects and ensure correct timing behavior.”
Frieder Heckmann, Valeo Schalter und Sensoren GmbH
Questions We Can Answer Right Away…
How much time do I need to create and maintain models?
Creating timing models is easier than you think. It takes only 30-60 minutes to define simple models. More complex models require a few days. We also recommend updating your models from time to time.
I already have a model of my system. Do I need to create a new model for chronSIM?
We recommend that everyone creates their first few models by hand in chronSIM. This is the easiest way to learn and understand the simulation environment.
Later on, models can be imported using our Python API, Excel import, or App4MC/AMALTHEA import.
Does chronSIM require source code access?
Simulations of the dynamic architecture with chronSIM are usually undertaken before any source code is available. chronSIM does not require access to source code. The models are defined at the abstraction level of the scheduler, tasks or processes, and functions.
Does chronSIM support my hardware?
chronSIM is independent of your target hardware. Execution times are usually defined in milliseconds/microseconds. This allows the functionality of any hardware to be defined. Regardless of the chosen CPU, µC, SoC, ECU, or system, it can be built within the integrated editor.
Does chronSIM support QNX, Linux, POSIX, and AUTOSAR adaptive platform?
Yes, chronSIM supports all of the above systems when using deterministic scheduling. Additionally, chronVIEW allows in-depth analysis of dynamic behavior based on RTOS-aware tracing when records of process state transitions and function entries and exits are available.
Does chronSIM support AUTOSAR?
Yes, chronSIM supports AUTOSAR classic and adaptive scheduling. Model information can be imported using our Python API. It should be noted that the required timing-relevant information is not stored in ARXML files.
Can I reuse data from other sources so that I don't have to start from scratch?
Yes, absolutely. chronSIM provides importers for a range of formats such as DBC, FIBEX, OIL, AUTOSAR XML, or APP4MC AMALTHEA. There is also a Python API available to write your own model generators.
What is the abstraction level of a timing model in chronSIM?
chronSIM supports modeling at different levels of abstraction such as logical, system, and software architecture level and the seamless transition from one level to the next as the project develops.
Can I model and analyze the behavior of complex event chains?
Yes. The metamodel supports the modeling of data dependencies and signal routing. For specific use cases, models can be extended using chronSIM’s C / C++ API.
Does chronSIM support end-to-end timing analysis?
Yes. With chronSIM you can analyze data flow and latencies in real-time systems starting at the sensor, across several vehicle buses and control units, through to an actuator.
chronVIEW supports visualization of the results from simulation and a range of hardware trace formats, including modern SoCs with multiple processors and hardware accelerators.
Can chronSIM be automated?
Yes, chronSIM supports batch-mode simulation and can be automated via command-line interface. It can be used on Windows or Linux, on a desktop PC or server, and in a cloud environment.
Full headless operation is also supported. It integrates with tools like Jenkins, Microsoft Azure, and many more.
“When using a hypervisor in domain controllers, it is advisable to use timing analysis during the design phase and continuous monitoring during development. This is both possible and efficient with INCHRON’s tools.“
Thomas Bock, Volkswagen AG,